Digital binary multipliers using full adders are well known, as disclosed in, e. g., U.S. Pat. Nos. 3,752,971, filed by D. F. Calhoun et al on Oct. 18, 1971; 4,130,878, filed by T. J. Balph et al on Apr. 3, 1978; 4,432,066, filed by N. F. Benschop on July 13, 1981; and 4,495,593, filed by F. A. Ware on July 1, 1982. Also, parallel multipliers using full adders are described in an article entitled "A GaAs 16.times.16 bit Parallel Multiplier" by Y. Nakayama et al in IEEE Journal of Solid-State Circuits, VOL. SC-18, NO. 5, October 1983, pp. 599-603. Furthermore, binary multipliers having inverting full adders are taught in U.S. Pat. Nos. 3,670,956, filed by D. F. Calhoun on Apr. 23, 1971 and 3,900,724, filed by G. W. McIver et al on Feb. 11, 1974. A ripple arithmetic logic unit (ALU) is disclosed in IBM Technical Disclosure Bulletin, Vol. 27 No. 6 November 1984, pp. 3214-3215, in an article entitled "Selective Powering of Ripple ALU for Improved Power Performance" by R. A. Bechade and an inverting full adder of the N channel metal oxide semiconductor (NMOS) type is disclosed in IBM Technical Disclosure Bulletin, Vol. 23 No. 11, April 1981, pp. 4870-4873, in an article entitled "Programmable Arithmetic/Logic Circuit" by R. A. Bechade and W. K. Hoffman. Adder or arithmetic circuits are also disclosed in U.S. Pat. No. 3,249,746 filed by W. A. Helig, et al, on Oct. 17, 1961 and in U.S. Pat. No 3,465,133 filed by R. K. Booher on June 7, 1966.
Although the digital binary multipliers disclosed in the hereinabove identified references satisfactorily provide the product of a multiplicand word and a multiplier word, the circuitry required to make these multipliers in integrated circuit form utilizes a relatively large amount of space on the surface of a semiconductor substrate or chip. Also, the circuitry used in these multipliers causes relatively large delays in their operation.